Semiconductor substrates or chips are commonly used in a variety of applications.
Semiconductor device manufacturing is typically divided into front end (FE) processes, which include steps for producing the semiconductor substrate of the device including its various components, and back end (BE) processes, which include assembling the substrate into some form of package.
Thus, during manufacture, after the FE production processes are completed, a back end (BE) production process, also called assembly, will follow. During known BE processes, the chip is taken out of a wafer semiconductor substrate whereon the chip is fabricated in vast numbers. This is known as singulation. Frequently the semiconductor chip is then encapsulated in a molding composition, creating a package, where die contacts of the active side of the semiconductor is routed to one nearby plane of the package for electrical connection. This package is mountable on a surface such as a printed circuit board (PCB). The packaged chip may be mounted together with other devices on the PCB, so as to provide for the electronic functionality of a particular product.
With the ongoing FE miniaturization the BE production process needs to keep up. Due to this miniaturization, not only do chips become smaller in area, but also an increased functionality is generally incorporated within this smaller area. The latter gives rise to more input and output signals as to channel and regulate the enhanced functionality. Ever more input and output signals on ever smaller silicon chip areas has in part lead to the strain in the BE process to keep up with miniaturization. Moreover, there are additional constraints on the BE process caused by a need for smaller footprints and smaller form factors (physical dimensions) of the semiconductor packages. This need stems from smaller and thinner end-products, for example tablet PC's, smart phones, multi media carriers and portable end-products. For these reasons the BE production process is under a continuous strain.
One of the recent advancements in this field (US 2011/0156237 A1) deals with the problem described above by routing electrically conductive interconnects from the die contacts to a pad ring located on the outer perimeter of one plane of the package as to maximize the usable surface available for surface bonding using solder balls.
Another advancement in this field (WO/2010/106515) deals with the structural aspects of how to create a small package which still maintains mechanical stability and reliability.
An important factor in these kinds of semiconductor packages is heat dissipation. As the functionality and the number of active devices in a chip increases, so does the heat dissipation requirement of the package used. Although this is very much dependant on the type of application, it can be seen that high frequency applications with increasing miniaturization at some point will test the boundaries, resulting in an increased junction temperature. This can seriously degrade the electronic functionality of the chip. It can introduce thermal noise or other nonlinear behavior if, for example, a large temperature gradient exists in the active area of the chip.
One method to remedy this is to attach a heat spreader on top of the package, enhancing the thermal dissipation of the package to the surrounding air. Another method is not to dissipate to air, but to the surface on which the package is mounted. This can be achieved by attaching one side of the heat spreader to the package and connecting the other side to the surface (e.g. PCB) thereby creating a thermal conduction path from the top of the package to the surface. Yet another way is by forced cooling, using a fan to force air over the package.
All these methods aid a reduction of the package temperature. However, the efficiency in substantially enhancing the thermal conductivity from the package to the surrounding environment is for some of these methods, limited. Additionally, some of these known methods are expensive and oftentimes incompatible with continual demands for ever smaller form factors of the package.
US2010/237471 describes a plurality of semiconductor dies mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening.
US 2009/039491 describes a semiconductor package including a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body.
US 2010/289095 describes a semiconductor device comprising a semiconductor chip defining a first face and a second face opposite to the first face, the semiconductor chip comprising at least one contact element on the first face of the semiconductor chip, an encapsulating body encapsulating the semiconductor chip, the encapsulating body having a first face and a second face opposite to the first face, a redistribution layer extending over the semiconductor chip and the first face of the encapsulating body and containing a metallization layer comprising contact areas connected with the contact elements of the semiconductor chip, an array of external contact elements located on the second phase of the encapsulating body.
Accordingly, a need exists for a better inherent thermal conductive coupling between a semiconductor package and the surface upon which it can be mounted.